The present invention relates generally to logic circuits and more particularly to powerful combinational N level high cascoding logic tree circuits with embedded supplemental logic functions in the inputs that are capable of processing complex Boolean logic functions with a high number of logic inputs.
The cascode current switch (CCS) logic circuit family is derived from the well known Emitter Coupled Logic (ECL) circuit family. ECL circuits are characterized by a systematic usage of non saturated transistors, resulting in high speed performances. Given the obvious power of the ECL logic circuits, the CCS logic circuits are the ideal candidates for being implemented in high end computers. The CCS logic circuit technology has potentially superior power-performance attributes compared to other logic circuit technologies. The cascode structure improves the logic efficiency of the circuit library, in that it allows a great variety of logic functions to be available to the user, but, at the cost of a more complex design system. As a whole, the CCS circuit technology still remains highly desirable because of its fast switching speeds. Cascode type of circuits can be classified in two main logic circuit families: the single ended cascode current switch (SECCS) circuit family, which uses accurate reference voltages, and the differential cascode current switch (DCCS) circuit family.
Several typical SECCS logic circuits are depicted in an article entitled "Simplified cascode reference generation" published in the IBM Technical Disclosure Bulletin Vol. 30 N.degree. 4 Sept. 1987 pp. 1816-1819. A basic circuit belonging to this family is shown in FIG. 1 of the present application. Circuit 10 is a standard six-input NAND circuit consisting of a central three-level cascode current switch logic tree 11, driving two emitter-follower circuits 12 and 13 to supply the complementary circuit output signals: respectively the IN PHASE and OUT OF PHASE circuit output signals. Logic tree 11 comprises bottom, top, and middle stages 14, 15, 16 dotted at the tree output nodes to perform a determined logic function. Basically, circuit 10 is made of three sets of current switches referenced 17, 18, and 19 mounted in a cascode configuration to form the logic tree 11. Each current switch comprises a pair of input transistors in parallel connected in a differential amplifier configuration with a reference transistor. The bottom stage at the first level comprises input transistors TX111 and TX112 connected in a differential amplifier configuration with reference transistor TX113. Input transistors TX111 and TX112 receive binary logic input signals All and A12 respectively, that are applied to the bases of said input transistors. The base of reference transistor TX113 is connected to a reference voltage VR11. At the second level, middle stage 15 comprises input transistors TX121 and TX122 driven by input signals B11 and B12, and reference transistor TX123, whose base is connected to reference voltage VR12. Finally, at third level, top stage 16 comprises input transistors TX131 and TX132 driven by input signals D11 and D12, and reference transistor TX133 whose base is connected to reference voltage VR13. The common collector of transistors TX131 and TX132 is connected to load RCCl. Collector of transistor TX133 is connected to load RCTl. These nodes correspond respectively to the tree output nodes referenced out and OUT. The bottom stage is supplied by a constant current IO, determined by a conventional current source comprised of transistor TY1, the base of which is connected to a fixed reference voltage VRR (delivered by a reference voltage generator not shown), and resistor RE. Said constant current IO given by relation IO=((VRR-VBE(TYl))/RE), has to flow either through transistors TX113 or TX111 and/or TX112. As a matter of fact, it flows through the one transistor which receives the highest base voltage. The collector voltage of transistors TX111 or TX112 may drop to a low value as soon as the current flows through input transistors TX111 or TX112. Similar reasoning applies to other levels. The constant current source IO sets the power that the logic tree 11 will consume in performing its assigned logical function. The logic operation is accomplished through selectively steering the current through an adequate path within the tree to one of the three output three output summation points at their respective stage that are referenced CN11, CN12 and CN13. These summation points correspond to the common emitter node of a pair of input transistors and the corresponding reference transistor. Current steering is accomplished by applying logic input signals to each input transistors in the tree, that will select the input transistors to be turned ON. The three sets of current switches in circuit 10 are connected so that, to get a low voltage on the OUT node, corresponding to a logical "0," the current has to flow one path only from top to bottom through TX133 or TX123 or TX113. Circuit 10 further includes one translator stage per output, respectively referenced 12 for the true output (IN PHASE signal) and 13 for the complement output (OUT OF PHASE signal). Translator 12 comprises buffer transistor TY2 connected in an emitter-follower configuration and driven by the signal supplied at node OUT. The true circuit output signal representing the logic function Fl performed by circuit 10, is available at output node T11 or T12. Diode SBD1 is used as a level shifter to shift down the voltage at node T12. Transistor TY3 and resistor RST act as a constant current source for translator 12. Similar construction applies to translator 13 for the complement circuit output signal F1 is available at node C11 or C12. Circuit 10 is biased between a first supply voltage, a positive voltage VPP=5V, and a second supply voltage, the ground GND. As a result, the logic Boolean function that is performed by circuit 10 is therefore Fl (All+A12).(B11+B12). (D11+D12). Other functions like extended ORs, Exclusive ORs (XORs), etc... may also be obtained by changing the connections between the different sets of current switches and the number of transistors contained therein.
The OAI logic circuit depicted in FIG. 1 is of the single ended type because, only the true binary input logic signals (e.g. All, A12, B11,...) are necessary. True input signals are applied to the bases of the input transistors, while the bases of other transistors so called reference transistors, are connected to a reference voltage (VR11, VR12, Circuit 10 comprises three cascode levels and works properly with VPP=5 V, but it is very doubtful that this circuit would operate satisfactorily with the very low supply voltages, e.g. VPP=3.4 V, that are used today in advanced computers. If three of more levels are necessary to increase the number of logical inputs, the conventional SECCS circuit of FIG. 1 would be no longer functional. As a result, the circuit library is limited in that respect. A significant improvement is described in copendinng European patent application EP-A-87489923 filed on 15 Dec. 1987 and assigned to the same assignee as of the present invention. Based on the teachings of that disclosure, FIG. 2 of the present application shows a two-two OA/OAI logic circuit referenced 20, with one three-input AND one two-input AND gates connected to the input transistors. Circuit 20 is derived from the conventional three-level single-ended cascode current switch (3L-SECCS) logic circuit 10 of FIG. 1. Similar/corresponding elements bear similar/corresponding references. With respect to circuit 10 of FIG. 1, two major changes have been implemented in circuit 20 of FIG. 2. First, the transistors composing the first level have been removed, being a potential source of non-functionality, when low supply voltages, e.g. VPP=3.4 V, are used, as mentioned above. Secondly, the bases of input transistors TX231 and TX232 of the top stage 26 are respectively provided with three and two level shifter devices, referenced SBD 21-22-23 and SBD 24-25 respectively; each level shifter is connected to a logic input signal referenced P21-22-23 and Q21-22, respectively. Preferably, level shifter devices are Schottky Barrier Diodes (SBD's). Level shifter devices move the voltages towards the more positive voltage VPP. The role of these extra input diodes in combination with respective resistors RD21 and RD22 is to perform an additional AND function on each of these input transistors, thus compensating the loss of the first level when the number of levels is above three. The logic function at the true output of circuit 20 is given by F2 (B21+B22) (P21.P22.P23 +Q21.Q22). Because connecting input diodes that way, adds more than one level of equivalent logic function, more logical functions can be implemented in one single logic tree. As a result, the circuit library is significantly enhanced. However, although improved, the SECCS logic circuit family, still suffer from some major drawbacks, specific to that technology, that prevents it from being more extensively used. The first drawback is the need for accurate reference voltage generators. Such generators need complex circuitry to attain the desired stability and consume extra silicon surface. In addition, the very high noise sensitivity of SECCS circuits is a problem for their integration in a mixed type of circuit environment such as the BICMOS. This is due to the high voltage swing necessary to maintain enough noise margin and thus to accept some voltage drops on power supplies and on the reference voltages. This is a severe inconvenience because the BICMOS technology, that offers the capability to mix bipolar ECL and CMOS FETs circuits on the same chip for optimization of the power-delay product, appears to have a very promising future. Still another drawback of the SECCS circuits is speed, SECCS circuits are not the fastest of the CCS circuit family. In view of all of these inconveniences, it may be worthwhile to use the other type of the CCS logic technology mentioned above: the so called Differential Cascode Current Switch (DCCS) circuit technology, although the latter has also some inherent limitations, that will be discussed thereafter.
Differential cascode current switch (DCCS) circuit technology is also well-known to those skilled in the art. Basic principles have been soon disclosed, for example, in an article entitled "Cascode parity circuit" by E. L. Carter et al. published in the IBM Technical Disclosure Bulletin Vol. 24 N.degree. 3 Aug. 1981 pp. 1705-1706. More details can be found in US-A-4760289 assigned to the same assignee as of the present invention. DCCS circuits may be easily derived from SECCS circuits, it suffices to remove one input transistor from the said pair and replace the said reference voltage that is applied to the reference transistor, by the appropriate complementary input. As a matter of fact, a conventional 3L-DCCS circuit performing a three-input AND/NAND function directly derived from circuit 10 of FIG. 1, is shown in FIG. 3 of the present application. Circuit 30 has a two branch structure and is typically implemented with NPN transistors and collector output usage. In the first level, bottom stage 34 consists of a current switch 37 comprising two input transistors TX311 and TX312 connected in a differential amplifier configuration, and driven respectively by binary input signals A31 and A31. Similar construction applies to the second and third stages 35 and 36, each of which also consist of a current switch referenced 38 and 39 respectively. Binary logic input signals B31, B31 and D31, D31 are respectively applied to said second and third stages. Function F3 is given by F3 =A31.B31.D31. DCCS tree 31 is therefore made of three stacked differential pairs of NPN transistor receiving IN PHASE and OUT OF PHASE logic input signals on their respective bases. The emitters or each pair of transistors are tied together to form a common emitter node. These nodes are respectively referenced CN31, CN32 and CN33 for the first, second and third levels respectively and correspond to the summation points of the logic tree. It is a characteristic feature of DCCS circuit 30 to have only two distinct branches at each stage. For example, in the third stage one branch comprises transistor TX331 and resistor RCC3, the other branch comprises transistor TX332 and resistor RCT, with the tree output nodes OUT and OUT respectively connected therebetween.
The tree offers only one path for the current IO defined in the lower part of the circuit by a current source comprised of transistor TYl and resistor RE. It is very important to notice that in DCCS circuit operation, only one transistor of the differential pair is ON, while the other is OFF. DCCS circuits are very high speed circuits because they operate with reduced voltage swings. In addition, they exhibit a relatively large noise immunity, because, the input signal is always compared to its complement. As a result, DCCS circuits are ideal candidates to be merged with CMOS circuits in a BICMOS single semiconductor chip, to speed up the critical data paths therein. However, the conventional DCCS circuits have also some drawbacks which have prevented them from becoming a generalized logic technology so far. For example, the major drawback of circuit 30 is the limited number of logic functions that can be implemented in the logic tree. This becomes more and more acute when low power supply voltages, e.g. 3.4 V, are used, as required for high end computers. With a 3.4 V power supply, only a maximum of three stages can be cascoded to implement circuit 30, to avoid functionality concerns. It is known by those skilled in the art, that the number of inputs in an AND circuit cannot exceeds the number of cascoded levels. If we suppose that the maximum of cascoded elements is three with a 3.4 to 3.6 V power supply, the Boolean function is then limited to three variables. As stated above, the cascode tree is defined by the stacking of three pairs of transistors to form the bottom, the middle and the top stages. Having in mind that only two paths are allowed by a pair of transistors, adding the middle stage offers four paths for the current with still only one path active at a time. Finally, adding the top stage to the structure permits a maximum of eight different path combinations. The conventional DCCS circuit family is thus limited to three-input AND/OR circuits at the maximum. As a consequence, DCCS circuits have a poor logic efficiency because the library of DCCS circuit is not as exhaustive as desired. In addition, the number of applications that can be derived from the DCCS circuit technology is also limited.
So there is a real need to date, of improving the conventional DCCS logic circuit technology is terms of logic efficiency, by adding supplemental AND/OR logic functions on the inputs of the circuits, while still keeping its inherent advantages, in particular in terms of speed and CMOS compatibility for BICMOS integration.
Therefore, it is a primary object of the present invention to provide a family of improved DCCS type logic circuits that are not limited to three levels of cascode due to the 3.4 V-3.6 V power supplies that are imposed to future bipolar technologies for high end computers.
It is another object of the present invention to provide a family of improved DCCS type logic circuits, functional down to the low supply voltage levels compatible with future CMOS products for BICMOS integration.
It is still another object of the present invention to provide family of improved DCCS type logic circuits wherein complex Boolean logic functions may be implemented with a high number of logic inputs at a very low cost.
It is still another object of the present invention to provide a family improved DCCS type logic circuits with a better power-performance product when compared with standard TTL/ECL logic gates.
It is still another object of the present invention to provide a family of improved DCCS type with a high number of logic inputs forming an exhaustive library of circuits, with a high number of logic functions available therein.
Basically, the present invention provides a family of logic circuits of the DCCS type including:
a logic tree formed by a plurality of stages cascoded and dotted to perform a determined logic function F between IN PHASE and OUT OF PHASE input signals (Z41, ... ;Z41, ...) and its complement F, at the tree output nodes in the top stage; wherein each stage of the current switch type basically consists of a pair of input transistors connected in a differential amplifier configuration, forming two independent branches and whose emitters are tied together to form a common emitter node;
a pair of load resistors to connect said output nodes to a first supply voltage;
a current source connected to a second supply voltage supplying a constant current to the common emitter node of the bottom stage of said logic tree;
CHARACTERIZED IN THAT at least one stage further includes:
first logic input means connected to the base of one input transistor driven by a first combination of said IN PHASE and OUT OF PHASE input signals to deliver a first elementary logic function on the common node of said stage; and,
second logic input means connected to at least one electrode of the other input transistor driven by a second combination of input signals, to deliver a second elementary logic function, complementary to said first function, on said common emitter node where these functions are summed up.